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1 ds9101-01 april 2011 www.richtek.com rt9101 ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pin configurations (top view) wdfn-8l 3x3 2.65w pwm class-d power amplifier features z z z z z wide operating voltage : 2.5v to 5.5v z z z z z high efficiency with an 8 speaker : ` ` ` ` ` 88% at 400mw ` ` ` ` ` 80% at 100mw z z z z z low quiescent current and shutdown current z z z z z optimized pwm output stage eliminates lc filter z z z z z fully differential design reduces rf rectification and eliminates bypass capacitor z z z z z internally generated 250khz switching frequency z z z z z integrated pop and click suppression circuitry z z z z z rohs compliant and halogen free applications z mobile phones z handsets z pdas z portable multimedia devices wl-csp-9b 1.45x1.45 (bsc) general description the rt9101 is a 2.65w, high efficiency class-d audio amplifier featuring low-resistance internal power mosfets and the gain can be set by an external input resistance. the filter free topology eliminates the output filter and reduces the external component count, footprint area, and system costs. operating from a single 5v supply, the rt9101 is capable of driving 4 speaker load at a continuous average output of 2.65w/10% thd+n or 2w/0.5% thd+n. the rt9101 has a higher efficiency with speaker load compared to a typical class ab amplifier. with a 3.6v supply driving an 8 speaker, the efficiency for a 400mw power level is 88%. it is very suitable for power sensitive application, such as cellular handsets and battery powered devices. in addition to these features, the rt9101 provides a fast startup time to minimize audible popping during device turn-on and turn- off. moreover, the rt9101 also integrates thermal and over current protection circuits. the rt9101 is available in wdfn-8l 3x3, and wl-csp-9b 1.45x1.45 (bsc) packages. inp inn outn gnd outp vdd gnd vdd a1 a2 a3 b3 b1 c1 c2 c3 b2 shdn nc inn outn gnd vdd outp inp 7 6 5 1 2 3 4 8 gnd 9 shdn rt9101 package type qw : wdfn-8l 3x3 (w-type) wsc : wl-csp-9b 1.45x1.45 (bsc) lead plating system g : green (halogen free and pb free) z : eco (ecological element with halogen free and pb free) () default : wdfn-8l 3x3 c : wl-csp-9b 1.45x1.45 (bsc)
2 ds9101-01 april 2011 www.richtek.com rt9101 typical application circuit figure 1. application circuit with differential input figure 2. application circuit with single-ended input marking information fl : product code ymdnn : date code 21 : product code w : date code fl ym dnn 21w rt9101gqw rt9101zqw fl=ym dnn fl= : product code ymdnn : date code rt9101cwsc inn outn gnd vdd outp inp rt9101 shdn r i c i r i c i c s 150k 150k 2.2f 2.2f audio input from dac 1f r l inn outn gnd vdd outp inp rt9101 shdn r i c i r i c i c s 150k 150k 2.2f 2.2f audio input 1f r l
3 ds9101-01 april 2011 www.richtek.com rt9101 function block diagram gate driver gate driver + - + - + - + - protection circuit inn outn gnd vdd outp inp shdn vdd functional pin description pin no. wdfn-8l 3x3 wl-csp-9b 1.45x1.45 (bsc) pin name pin function 1 c2 shdn shutdown control (active low). 2 -- nc no internal connection. 3 a1 inp positive input of differential audio signal. 4 c1 inn negative input of differential audio signal. 5 c3 outp positive output. 6 b1, b2 vdd supply voltage input. 7, 9 (exposed pad) a2, b3 gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum thermal dissipation. 8 a3 outn negative output.
4 ds9101-01 april 2011 www.richtek.com rt9101 electrical characteristics (v dd = 5v, t a = 25 c, unless otherwise specified) absolute maximum ratings (note 1) z supply voltage, v dd ------------------------------------------------------------------------------------------------- ? 0.3v to 6v z input voltage, inp, inn ---------------------------------------------------------------------------------------------- ? 0.3v to(v dd + 0.3v) z power dissipation, p d @ t a = 25 c wdfn-8l 3x3 --------------------------------------------------------------------------------------------------------- 1.429w wl-csp-9b 1.45x1.45 (bsc) ------------------------------------------------------------------------------------- 1.250w z package thermal resistance (note 2) wdfn-8l 3x3, ja ---------------------------------------------------------------------------------------------------- 70 c/w wdfn-8l 3x3, jc --------------------------------------------------------------------------------------------------- 8.2 c/w wl-csp-9b 1.45x1.45 (bsc), ja ------------------------------------------------------------------------------- 80 c/w z junction temperature ------------------------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) ----------------------------------- --------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------- 200v recommended operating conditions (note 4) z supply voltage, v dd ------------------------------------------------------------------------------------------------- 2.7v to 5.5v z junction temperature range --------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range --------------------------------------------------------------------------------------- ? 40 c to 85 c parameter symbol test conditions min typ max unit output offset voltage v os v dd = 2.5v to 5.5v -- 1 25 mv power supply rejection ratio psrr v dd = 2.5v to 5.5v (note 5) -- ? 70 ? 55 db high level input current ? i ih ? v dd = 5.5v, vi = 5.8v -- -- 100 a low level input current ? i il ? v dd = 5.5v, vi = ? 0.3v -- -- 5 a logic-high v ih 2 -- -- shdn input threshold voltage logic-low v il -- -- 0.4 v v dd = 5.5v, no load -- 3.4 4.9 v dd = 3.6v, no load -- 2.8 -- quiescent current i q v dd = 2.5v, no load -- 2.2 3.2 ma shutdown current i shdn v shdn = 0v, v dd = 2.5v to 5.5v -- -- 1 a v dd = 2.5v -- 600 -- v dd = 3.6v -- 500 -- static drain-source on-state resistance r ds(on) v dd = 5v -- 400 -- m output impedance in shdn v shdn = 0v -- >1 -- k switching frequency v dd = 2.5v to 5.5v 200 250 300 khz gain v dd = 2.5v to 5.5v 284k/r i 300k/r i 316k/r i v/v resistance from shdn to gnd -- 200 -- k to be continued
5 ds9101-01 april 2011 www.richtek.com rt9101 note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high-effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. guarantee by design. operating characteristics (gain = 2v/v,r l = 8 , t a = 25 c, unless otherwise noted) parameter symbol test condition min typ max unit v dd = 5v -- 2.65 -- v dd = 3.6v -- 1.5 -- thd+n = 10%, f = 1khz, r l = 4 v dd = 2.5v -- 0.52 -- w v dd = 5v -- 2.08 -- v dd = 3.6v -- 1.06 -- thd+n = 1%, f = 1khz, r l = 4 v dd = 2.5v -- 0.42 -- w v dd = 5v -- 1.45 -- v dd = 3.6v -- 0.73 -- thd+n = 10%, f = 1khz, r l = 8 v dd = 2.5v -- 0.33 -- w v dd = 5v -- 1.19 -- v dd = 3.6v -- 0.59 -- output power p o thd+n = 1%, f = 1khz, r l = 8 v dd = 2.5v -- 0.26 -- w v dd = 5v, p o = 1w, r l = 8 , f = 1khz -- 0.06 -- v dd = 3.6v, p o = 0.5w, r l = 8 , f = 1khz -- 0.05 -- total harmonic distortion plus noise thd+n v dd = 2.5v, p o = 200mw, r l = 8 , f = 1khz -- 0.04 -- % supply ripple rejection ratio psrr v dd = 5v, f = 217hz, v dd-ripple = 200mvpp -- ? 70 -- db signal-to-noise ratio snr v dd = 5v, p o = 1w, r l = 8 , a weighting filter -- 95 -- db input impedance z i 142 150 158 k start-up time from shutdown v dd = 3.6v -- 1 -- ms
6 ds9101-01 april 2011 www.richtek.com rt9101 typical operating characteristics output power vs. load resistance 0.0 0.5 1.0 1.5 2.0 2.5 4 8 12 16 20 24 28 32 load resistance (db) output power (w) v dd = 5v gain = 2v/v, f = 1khz, thd+n = 10% v dd = 2.5v v dd = 3.6v output power vs. load resistance 0.0 0.5 1.0 1.5 2.0 2.5 4 8 12 16 20 24 28 32 load resistance (db) output power (w) v dd = 5v gain = 2v/v, f = 1khz, thd+n = 1% v dd = 2.5v v dd = 3.6v efficiency vs. output power 0 10 20 30 40 50 60 70 80 90 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 output power (w) efficiency (%) v dd = 5v gain = 2v/v, f = 1khz, r l = 4 , 33 h v dd = 2.5v v dd = 3.6v efficiency vs. output power 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 1.2 output power (w) efficiency (%) v dd = 5v gain = 2v/v, f = 1khz, r l = 8 , 33 h v dd = 2.5v v dd = 3.6v supply current vs. output power 0 100 200 300 400 500 600 700 00.511.522.53 output power (w) supply current (ma) v dd = 5v gain = 2v/v, r l = 4 , 33 h v dd = 2.5v v dd = 3.6v supply current vs. output power 0 50 100 150 200 250 300 0 0.2 0.4 0.6 0.8 1 1.2 1.4 output power (w) supply current (ma) v dd = 5v gain = 2v/v, r l = 8 , 33 h v dd = 2.5v v dd = 3.6v
7 ds9101-01 april 2011 www.richtek.com rt9101 r l = 4 , f = 1khz, gain = 2v/v thd+n vs. output power 10m 20m 50m 100m 200m 500m 1 2 5 thd+n (%/div) output power (w/div) 20 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 v dd = 2.5v v dd = 3.6v v dd = 5v thd+n vs. frequency 20 50 100 200 500 1k 2k 5k 10k 20k thd+n (%/div) frequency (hz/div) p o = 50mw p o = 250mw p o = 1w v dd = 5v, c i = 2.2 f, r l = 8 , gain = 2v/v 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 thd+n vs. frequency 20 50 100 200 500 1k 2k 5k 10k 20k frequency (hz/div) p o = 25mw p o = 125mw p o = 500mw thd+n (%/div) v dd = 3.6v, c i = 2.2 f, r l = 8 , gain = 2v/v 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 thd+n vs. frequency 20 50 100 200 500 1k 2k 5k 10k 20k thd+n (%/div) frequency (hz/div) p o = 15mw p o = 75mw p o = 200mw v dd = 2.5v, c i = 2.2 f, r l = 8 , gain = 2v/v 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 thd+n vs. frequency 20 50 100 200 500 1k 2k 5k 10k 20k thd+n (%/div) frequency (hz/div) v dd = 2.5v v dd = 3.6v v dd = 5v v dd = 4v p o = 250mw, c i = 2.2 f, r l = 4 , gain = 2v/v 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 r l = 8 , f = 1khz, gain = 2v/v thd+n vs. output power 10m 20m 50m 100m 200m 500m 1 2 5 thd+n (%/div) output power (w/div) 20 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 v dd = 2.5v v dd = 3.6v v dd = 5v
8 ds9101-01 april 2011 www.richtek.com rt9101 power dissipation vs. output power 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 00.511.522.5 output power (w) power dissipation (w) r l = 8 + 33 h v dd = 5v, f = 1khz, gain = 2v/v r l = 4 + 33 h power dissipation vs. output power 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0.2 0.4 0.6 0.8 1 1.2 output power (w) power dissipation (w) r l = 8 + 33 h v dd = 3.6v, f = 1khz, gain = 2v/v r l = 4 + 33 h gsm power supply rejection vs. time gain = 2v/v, c i = 2.2 f, r l = 8 , f = 217hz, duty = 12% time (2.5ms/div) v dd (1v/div) v out (20mv/div) v dd = 3.6v, p k -p k = 512mv gsm power supply rejection vs. frequency 0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k (db/div) frequency (hz/div) +0 -20 -40 -60 -80 -100 -120 -140 -150 supply voltage output voltage v dd = 3.6v, c i = 2.2 f, r l = 8 , gain = 2v/v psrr vs. frequency 20 50 100 200 500 1k 2k 5k 10k 20k psrr (db/div) frequency (hz/div) +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 v dd = 2.5v v dd = 3.6v v dd = 5v v p-p = 200mv, c i = 2.2 f, r l = 4 , gain = 2v/v psrr vs. frequency 20 50 100 200 500 1k 2k 5k 10k 20k psrr (db/div) frequency (hz/div) +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 v dd = 2.5v v dd = 3.6v v dd = 5v v p-p = 200mv, c i = 2.2 f, r l = 8 , gain = 2v/v
9 ds9101-01 april 2011 www.richtek.com rt9101 application information the rt9101 is a fully differential amplifier with differential inputs and outputs. the rt9101 integrates a differential amplifier and a common mode voltage controller. the differential amplifier ensures that the amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. the rt9101 can support differential input and single ended input applications. components selection input resistors (r i ) amplifier can be resistors and the gain can be calculated as the following equation : resistor matching is very important in fully differential amplifiers. the balance of the output on the reference voltage depends on matched ratios of the input resistors. cmrr, psrr, and the cancellation of the second harmonic distortion diminish if resistor mismatch occurs. therefore, it is recommended to use 1% tolerance or better resistors to keep the performance optimized. the input resistors should be placed very close to the rt9101 to limit noise injection on the high impedance nodes. it is recommended to set the gain at 2v/v or lower for better performance. decoupling capacitor the rt9101 is a high performance class-d audio amplifier that requires adequate power supply decoupling to ensure the efficiency is high and total harmonic distortion (thd) is low. for higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (esr) ceramic capacitor, typically 1 f, placed as close as possible to the vdd pin can achieve the best performance. placing this decoupling capacitor close to the rt9101 is very important for the efficiency of the class- d amplifier, because any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. for filtering lower frequency noise signals, it is recommended to use a 10 f or greater capacitor placed near the audio power amplifier. input capacitor in the typical application, an input coupling capacitor (c i ) is required to allow the input signal to the proper dc level for optimum operation. however, the rt9101 is a fully differential amplifier with good cmrr so that the rt9101 does not require input coupling capacitors if using a differential input source that is biased from 0.5 v to vdd ? 0.8 v. use 1% tolerance or better gain-setting resistors if input coupling capacitors are not used. in the single-ended input application, a n input capacitor, (c i ), is required to allow the amplifier to bias the input signal to the proper dc level. in this case, c i and r i form a high-pass filter with the corner frequency as shown in the following equation : c ii 1 f 2rc = f (hz) f c -3db gain (db) the value of c i is important to consider as it directly affects the bass (low frequency) performance of the circuit. for example, the flat bass response requirement is 10 hz and r i is 20k , the value of c i can be calculated by the following equation : i ic 1 c 2rf = in this example, c i is 0.8 f. a capacitance1 f or larger can be used. under voltage lockout the under voltage lock out circuit operates as a voltage detector and alwa ys monitors the supply voltage (vdd) while shnd = 1. while powered on, the chip is kept still in shutdown mode until vdd rises to greater than 2.2v (typ). while powered off, the chip does not leave operation mode until vdd falls to less than 2. 1v (typ). i 2 x 150k gain = r
10 ds9101-01 april 2011 www.richtek.com rt9101 layout considerations for best performance of the rt9101, the following pcb layout guidelines must be strictly followed. ` place the decoupling capacitors as close as possible to the vdd and gnd pins. ` keep the differential input and output traces as wide and short as possible. the traces of (inp & inn) and (outp & outn) should be kept equal width and length respectively. ` connect the gnd and exposed pad to a strong ground plane for maximum thermal dissipation and noise protection. figure 4. pcb layout guide nc inn outn gnd vdd outp inp 7 6 5 1 2 3 4 8 gnd 9 shdn c s r i c i r i c i audio input the decoupling capacitor (c s ) must be placed as close to the ic as possible gnd thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the rt9101, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for wdfn- 8l 3x3 packages, the thermal resistance, ja , is 70 c/w on a standard jedec 51-7 four-layer thermal test board. for wl-csp-9b 1.45x1.45 (bsc) packages, the thermal resistance, ja , is 80 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (70 c/w) = 1.429w for wdfn-8l 3x3 package p d(max) = (125 c ? 25 c) / (80 c/w) = 1.250w for wl-csp-9b 1.45x1.45 (bsc) package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the rt9101 packages, the derating curves in figure 3 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 3. derating curves for rt9101 packages 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb wdfn-8l 3x3 wl-csp-9b 1.45x1.45 (bsc)
11 ds9101-01 april 2011 www.richtek.com rt9101 outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 2.950 3.050 0.116 0.120 d2 2.100 2.350 0.083 0.093 e 2.950 3.050 0.116 0.120 e2 1.350 1.600 0.053 0.063 e 0.650 0.026 l 0.425 0.525 0.017 0.021 w-type 8l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a
12 ds9101-01 april 2011 www.richtek.com rt9101 richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com 9b wl-csp 1.45x1.45 package (bsc) symbol dimensions in millimeters dimensions in inches min max min max a 0.525 0.625 0.021 0.025 a1 0.200 0.260 0.008 0.010 b 0.290 0.350 0.011 0.014 d 1.400 1.500 0.055 0.059 d1 1.000 0.039 e 1.400 1.500 0.055 0.059 e1 1.000 0.039 e 0.500 0.020

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